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FEATURES < 2 ns Rise/Fall Times Output Current: 120 mA Single +5 V Power Supply Switching Rate: 200 MHz typ Onboard Light Power Control Loop APPLICATIONS Laser Printers and Copiers GENERAL DESCRIPTION
Laser Diode Driver with Light Power Control AD9661A
and fall times are 2 ns to complement printer applications that use image enhancing techniques such as pulse width modulation to achieve gray scale and resolution enhancement. Control signals are TTL/CMOS compatible. The driver output provides up to 120 mA of current into an infrared N type laser, and the onboard disable circuit turns off the output driver and returns the light power control loop to a safe state. The AD9661A can also be used in closed-loop applications in which the output power level follows an analog POWER LEVEL voltage input. By optimizing the external hold capacitor and the photo detector, the loop can achieve bandwidths as high as 25 MHz. The AD9661A is offered in a 28-pin plastic SOIC for operation over the commercial temperature range (0C to +70C).
The AD9661A is a highly integrated driver for laser diode applications such as printers and copiers. The AD9661A gets feedback from an external photo detector and includes an analog feedback loop to allow users to set the power level of the laser, and switch the laser on and off at up to 100 MHz. Output rise
FUNCTIONAL BLOCK DIAGRAM
DISABLE PULSE PULSE2 CAL
TTL TTL
DISABLE CIRCUIT
*13ns DELAY ON RISING EDGE; 0ns ON FALLING HOLD
TTL TTL DELAY
*
VOLT REF
VREF
+5V
PHOTO DETECTOR
POWER LEVEL LEVEL SHIFT OUT LEVEL SHIFT IN DAC GAIN CGAIN RGAIN
ANALOG VLEVEL SHIFT IN + VREF 5pF LEVEL SHIFT CIRCUIT 0-1.6V 50
V1 1:10 REF
3-120mA IOUT
LASER DIODE
OUTPUT
8
AD9661A
ANALOG POWER MONITOR VREF
IMONITOR
1:1
SENSE IN IMONITOR 1.0V
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD9661A-SPECIFICATIONS (+V = +5 V, Temperature = +25 C unless otherwise noted)
S
Parameter ANALOG INPUT Input Voltage Range, POWER LEVEL Input Bias Current, POWER LEVEL Analog Bandwidth, Control Loop1 Input Voltage Range, LEVEL SHIFT IN Input Bias Current, LEVEL SHIFT IN Analog Bandwidth, Level Shift2 Level Shift Offset Level Shift Gain OUTPUTS Output Current, IOUT Output Compliance Range Idle Current Disable Current SWITCHING PERFORMANCE Maximum Pulse Rate Output Propagation Delay (tPD), Rising3 Output Propagation Delay (tPD), Falling3 Output Current Rise Time4 Output Current Fall Time5 CAL Aperture Delay6 Disable Time7 HOLD NODE Input Bias Current Input Voltage Range Minimum External Hold Cap TTL/CMOS INPUTS Logic "1" Voltage Logic "1" Voltage Logic "0" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current
8
Test Level Temp
Min
AD9661AKR Typ Max
Units
Conditions
IV I V IV I V I I I IV I IV V IV IV IV IV IV IV I IV V I IV I IV I I I V V I I V I I
Full +25C +25C Full +25C Full +25C +25C +25C +25C +25C +25C +25C Full Full Full Full Full +25C +25C Full Full +25C Full +25C Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C
VREF -50 25 0.1 -10 130 -32 0.95 120 2.50 2 1.0
VREF + 1.6 +50 1.6 0 +32 1.05
V A MHz V A MHz mV V/V mA V mA A MHz ns ns ns ns ns ns nA V pF V V V V A mA V mV/C mA mA/mA V V mA
CHOLD = 33 pF, RF = 1 k, CF = 2 pF
VOUT = 2.5 V PULSE = LOW, DISABLE = LOW PULSE = LOW, DISABLE = HIGH Output Current -3 dB
5.25 5.0 1.0
2.9 3.2
200 3.9 3.7 1.5 1.5 13 3
5.0 4.3 2.0 2.0 5 200 VREF + 1.6
-200 VREF 25 2.0 2.0
VHOLD = 2.5 V Open-Loop Application Only
-10 -1.5 1.6 -0.5 0.95 0.7 1 1.0 <150 5.00 75 1.8 -0.1
0.8 0.8 10
VHIGH = 5.0 V VLOW = 0.8 V
BANDGAP REFERENCE Output Voltage (VREF) Temperature Coefficient Output Current SENSE IN Current Gain Voltage Input Resistance POWER SUPPLY +VS Voltage +VS Current
1.9 1.0 1.02 1.3
4.75 60
5.25 95
DISABLE = HIGH, VHOLD = VREF, VS = 5.0 V
NOTES 1 Based on rise time of closed-loop pulse response. See Performance Curves. 2 Based on rise time of pulse response. 3 Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to the 50% point of the rising/falling edge of the output modulation current. 4 Rise time measured between the 10% and 90% points of the rising transition of the modulation current. 5 Fall time measured between the 10% and 90% points of the falling transition of the modulation current. 6 Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is held during this test. 7 Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable is similar to fall time during normal operation. 8 PULSE, PULSE2, DISABLE, and CAL are TTL/CMOS compatible inputs. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS*
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V POWER LEVEL, LEVEL SHIFT IN . . . . . . . . . . . 0 V to +VS TTL/CMOS INPUTS . . . . . . . . . . . . . . . . . . . . -0.5 V to +VS Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Operating Temperature AD9661AKR . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . +150C Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300C
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
EXPLANATION OF TEST LEVELS Test Level
I - 100% production tested. II - 100% production tested at +25C, and sample tested at specified temperatures. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C; 100% production tested at temperature extremes for military devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERING GUIDE
Model
Temperature Range Package Option R-28 R-28 (1000/Reel)
+VS 1mA 1mA +VS
AD9661AKR 0C to +70C AD9661AKR-REEL 0C to +70C
+VS
VBANDGAP TTL INPUT
100 VREF 450
SENSE IN
50
50
1250
OUTPUT
HOLD
T/H
Equivalent Circuits
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9661A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN DESCRIPTIONS
Pin OUTPUT POWER LEVEL
Function Analog laser diode current output. Connect to cathode of laser diode, anode connected to +VS externally. Analog voltage input, VREF to VREF + 1.6 V. Output current is set proportional to the POWER LEVEL V POWER LEVEL - VREF during calibration as follows: I MONITOR = RGAIN + 50 TTL/CMOS compatible, feedback loop T/H control signal. Logic LOW enables calibration mode, and the feedback loop T/H goes into track mode 13 ns after (the aperture delay) PULSE goes logic HIGH (there is no aperture delay if PULSE goes high before CAL transitions to a LOW level). Logic HIGH disables the T/H and immediately places it in hold mode. PULSE should be held HIGH while calibrating. Floats logic HIGH. External hold capacitor for the bias loop T/H. Approximate droop in the output current while CAL is -9 18 x 10 t HOLD IOUT = logic HIGH is: CHOLD Bandwidth of the loop is: BW 2 (550 ) C HOLD
CAL
HOLD
1
PULSE PULSE 2 SENSE IN
GAIN
POWER MONITOR DISABLE
VREF +VS GROUND LEVEL SHIFT IN LEVEL SHIFT OUT
TTL/CMOS compatible, current control signal. Logic HIGH supplies I OUT to the laser diode. Logic LOW turns I OUT off. Floats logic HIGH. TTL/CMOS compatible, current control signal. Logic LOW supplies IOUT to the laser diode. Logic HIGH turns I OUT off. Floats logic HIGH. Analog current input, IMONITOR, from PIN photo detector diode. SENSE IN should be connected to the anode of the PIN diode, with the PIN cathode connected to +VS or another positive voltage. Voltage at SENSE IN varies slightly with temperature and current, but is typically 1.0 V. External connection for the feedback network of the transimpedance amplifier. External feedback network, RGAIN and CGAIN, should be connected between GAIN and POWER MONITOR. See text for choosing values. Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo diode, IMONITOR. TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to VREF (minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH. Analog Voltage output, internal bandgap voltage reference, ~1.8 V, provided to user for power level offset. Power Supply, nominally +5 V. All +VS connections should be tied together externally. Ground reference. All GROUND connections should be tied together externally. Analog input to the on board level shift circuit. Input Range 0.1 V - 1.6 V. Voltage output from on board level shift circuit. Connect to POWER LEVEL externally to use the on board level shift circuit. Output voltage is VLEVEL SHIFT OUT = VLEVEL SHIFT IN +VREF.
PIN ASSIGNMENTS
PULSE2 DNC VREF 1 2 3 28 +VS 27 GROUND 26 OUTPUT 25 GROUND 24 OUTPUT
LEVEL SHIFT IN 4 GAIN 5 POWER MONITOR SENSE INPUT GROUND +VS 6 7 8 9
AD9661AKR
(Not to Scale)
23 GROUND 22 OUTPUT 21 GROUND 20 OUTPUT 19 GROUND 18 +VS 17 GROUND 16 CAL 15 PULSE1
GROUND 10 HOLD 11 POWER LEVEL 12 LEVEL SHIFT OUT 13 DISABLE 14
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THEORY OF OPERATION Control Loop Transfer Function
The AD9661A combines a very fast output current switch with an onboard analog light power control loop to provide the user with a complete laser diode driver solution. The block diagram illustrates the key internal functions. The control loop of the AD9661A adjusts the output current level, IOUT, so that the photo diode feedback current, IMONITOR, into SENSE IN is proportional to the analog input voltage at POWER LEVEL. Since the monitor current is proportional to the laser diode light power, the loop effectively controls laser power to a level proportional to the analog input. The control loop should be periodically calibrated (see Choosing CHOLD). The disable circuit turns off IOUT and returns the hold capacitor voltages to their minimum levels (minimum output current) when DISABLE = logic HIGH. It is used during initial power up of the AD9661A or during time periods where the laser is inactive. When the AD9661A is re-enabled the control loop must be recalibrated. Normal operation of the AD9661A involves the following (in order, see Figure 1): 1. The AD9661A is enabled (DISABLE = logic LOW). 2. The input voltage (POWER LEVEL) is driven to the appropriate level to set the calibrated laser diode output power level. 3. The feedback loop is closed for calibration (CAL = logic LOW, and PULSE = logic HIGH), and then opened (CAL = logic HIGH). 4. While the feedback loop is open, the laser is pulsed on and off by PULSE. 5. The feedback loop is periodically recalibrated as needed. 6. The AD9661A is disabled when the laser will not be pulsed for an indefinite period of time.
The relationship between IMONITOR and VPOWER LEVEL is
I MONITOR = VPOWER LEVEL -V REF (RGAIN + 50 )
once the loop is calibrated. When the loop is open (CAL = logic HIGH), the output current, IOUT, is proportional to the held voltage at HOLD; the external hold capacitor on this pin determines the droop error in the output current between calibrations. The sections below discuss choosing the external components in the feedback loop for a particular application.
Choosing RGAIN
The gain resistor, RGAIN, allows the user to match the feedback loop's transfer function to the laser diode/photo diode combination. The user should define the maximum laser diode output power for the intended application, PLD MAX, and the corresponding photo diode monitor current, IMONITOR MAX. A typical laser diode transfer function is illustrated below. RGAIN should be chosen as: 1.6V RGAIN = - 50 I MONITOR MAX
4 0C CASE
OPTICAL OUTPUT - mW
3
CONSTANT WRITE POWER 2
25C CASE 50C CASE
1
0
0
20
40 60 80 FORWARD CURRENT - mA IOUT
100
120
Figure 2. Laser Diode Current-to-Optical Power Curve
DISABLE
POWER-UP OR LASER NOT IN USE CAL TIME RECALIBRATE HOLD TIME
CAL
PULSE LASER POWER MODULATED CALIBRATED LEVEL LASER OUTPUT POWER
Figure 1. Normal Operating Mode
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The laser diode's output power will then vary from 0 to PLD MAX for an input range of VREF to VREF +1.6 V @ the POWER LEVEL input. Minimum specifications for IMONITOR MAX should be used when choosing RGAIN. Users are cautioned that laser diode/photo diode combinations that produce monitor currents that are less than IMONITOR MAX in the equation above will produce higher laser output power than predicted, which may damage the laser diode. Such a condition is possible if RGAIN is calculated using typical instead of minimum monitor current specifications. In that case the input range to the AD9661A POWER LEVEL input should be limited to avoid damaging laser diodes. Another approach would be to use a potentiometer for RGAIN. This allows users to optimize the value of RGAIN for each laser diode/photo diode combination's monitor current. The drawback to this approach is that potentiometers' stray inductance and capacitance may cause the transimpedance amplifier to overshoot and degrade its settling, and the value of CGAIN may not be optimized for the entire potentiometer's range. CGAIN optimizes the response of the transimpedance amplifier and should be chosen as from the table below. Choosing CGAIN larger than the recommended value will slow the response of the amplifier. Lower values improve TZA bandwidth but may cause the amplifier to oscillate.
Table I.
To choose a value, the user will need to determine the amount of time the loop will be in hold mode, t HOLD, the maximum change in laser output power the application can tolerate, and the laser efficiency (defined as the change in laser output power to the change in laser diode current). As an example, if an application requires 5 mW of laser power 5%, and the laser diode efficiency is 0.25 mW/mA, then
mW I MAX = 5 mW x(5%)/ 0.25 =1.0 mA mA
If the same application had a hold time requirement of 250 s, then the minimum value of the hold capacitor would be:
CHOLD =
18 x10 -9 x 250 s = 4.5 nF 1.0 mA
When determining the calibration time, the T/H and the external hold capacitor can be modeled using the simple RC circuit illustrated below.
AD9661A
POWER LEVEL T/H CHOLD EXTERNAL HOLD CAPACITOR R
HOLD
RGAIN 2.5 k 1.5 k 1 k 500
Choosing CHOLD
Recommended CGAIN 2 pF 3 pF 4 pF 8 pF
POWER MONITOR
TZA
Figure 3. Circuitry Model for Determining Calibration Times
Using this model, the voltage at the hold capacitor is
Choosing values for the hold capacitor, CHOLD, is a tradeoff between output current droop when the control loop is open, and the time it takes to calibrate and recalibrate the laser power when the loop is closed. The amount of output current droop is determined by the value of the hold capacitor and the leakage current at that node. When the control loop is open (CAL logic HIGH), the pin connection for the hold capacitor (HOLD) is a high impedance input. Leakage current will range from 200; this low current minimizes the droop in the output power level. Assuming the worst case current of 200 nA, the output current will change as follows: IOUT = 18 x 10
-9
-t VCHOLD =V t = 0 +(V t = -Vt = 0 )1- e
where t = 0 is when the calibration begins (CAL goes logic LOW), Vt = 0 is the voltage on the hold cap at t = 0, Vt = is the steady state voltage at the hold cap with the loop closed, and = RCHOLD is the time constant. With this model the error in VCHOLD for a finite calibration time, as compared to Vt = , can be estimated from the following table and chart:
Table II.
tCALIBRATION 7 6 5 4 3 2
% Final Value 99.9 99.7 99.2 98.1 95.0 86.5 63.2
Error % 0.09 0.25 0.79 1.83 4.97 13.5 36.8
CHOLD
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100 90
Driving the Analog Inputs
% FINAL VALUE - % of Volts
80 70 60 50 40 30 20 10 0 0 1 2 3 4 5
The POWER LEVEL input of the AD9661A drives the track and hold amplifier and allows the user to adjust the amount of output current as described above. The input voltage range is VREF to VREF + 1.6 V, requiring the user to create an offset of VREF for a ground based signal (see below for description of the on board level shift circuit). The circuit below will perform the level shift and scale the output of a DAC whose output is from ground to a positive voltage. This solution is especially attractive because both the DAC and the op amp can run off a single +5 V supply, and the op amp doesn't have to swing rail to rail.
VREF + VDAC R2 =V R1 POWER LEVEL R2 VDAC R1 DAC R2 VREF R1 +5V OP191 BIAS LEVEL
AD9661A
TIME CONSTANTS -
Figure 4. Calibration Time
Initial calibration is required after power-up or any other time the laser has been disabled. Disabling the AD9661A drives the hold capacitor to VREF. In this case, or in any case where the output current is more than 10% out of calibration, R will range from 300 to 550 for the model above; the higher value should be used for calculating the worst case calibration time. Following the example above, if CHOLD were chosen as 4.5 nF, then = RC = 550 x 4.5 nF would be 2.48 s. For an initial calibration error < 1%, the initial calibration time should be > 5 = 12.36 s. Initial calibration time will actually be better than this calculation indicates, as a significant portion of the calibration time will be within 10% of the final value, and the output resistance in the AD9660's T/H decreases as the hold voltage approaches its final value. Recalibration is functionally identical to initial calibration, but the loop need only correct for droop. Because droop is assumed to be a small percentage of the initial calibration (< 10%), the resistance for the model above will be in the range of 75 to 140 . Again, the higher value should be used to estimate the worst case time needed for recalibration. Continuing with the example above, since the droop error during hold time is < 5%, we meet the criteria for recalibration and = RC = 140 x 4.5 nF = 0.64 s. To get a final error of 1% after recalibration, the 5% droop must be corrected to within a 20% error (20% x 5% = 1%). A 2 recalibration time of 1.2 s is sufficient.
Continuous Recalibration
Figure 5. Driving the Analog Inputs
Using the Level Shift Circuit
The AD9661A includes an on board level shift circuit to provide the offset described above. The input, LEVEL SHIFT IN, has an input range from 0.1 V to 1.6 V. The output, LEVEL SHIFT OUT, has a range from VREF to VREF +1.6 V, and can drive POWER MONITOR. The linearity of the level shift circuit is poor for inputs below 100 mV. Between 100 mV and 1.6 V it is about 7 bits accurate.
Layout Considerations
As in all high speed applications, proper layout is critical; it is particularly important when both analog and digital signals are involved. Analog signal paths should be kept as short as possible, and isolated from digital signals to avoid coupling in noise. In particular, digital lines should be isolated from OUTPUT, SENSE IN, POWER LEVEL, LEVEL SHIFT IN POWER MONITOR, and HOLD traces. Digital signal paths should also be kept short, and run lengths matched to avoid propagation delay mismatch. Layout of the ground and power supply circuits is also critical. A single, low impedance ground plane will reduce noise on the circuit ground. Power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit. 0.1 F surface mount capacitors, placed as close as possible to the AD9661A +VS connections, and the +VS connection to the laser diode meet this requirement. Multilayer circuit boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance power planes to further reduce noise.
In applications where the hold capacitor is small (< 500 pF) and the WRITE PULSE signals always have a pulse width > 25 ns, the user may continuously calibrate the feedback loop. In such an application, the CAL signal should be held logic LOW, and the PULSE signal will control loop calibration via the internal AND gate. In such application, it is important to optimize the layout for the TZA (POWER MONITOR, GAIN, RGAIN and CGAIN).
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Minimizing the Impedance of the Output Current Path Optimizing the Feedback Layout
Because of the very high current slew that the AD9661A is capable of producing (120+ mA in 1.5 ns), the inductance of the output current path to and from the laser diode is critical. A good layout of the output current path will yield high quality light pulses with rise times of about 1.5 ns and less than 5% overshoot. A poor layout can result in significant overshoot and ringing. The most important guideline for the layout is to minimize the impedance (mostly inductance) of the output current path to the laser. It is important to recognize that the laser current path is a closed loop. The figure illustrates the path that current travels: (1) from the +VS connection at the anode of the laser to the cathode (2) from the cathode to the output pins of the AD9661A (3) through the output drive circuit of the AD9661A, (4) through the return path (GROUND plane in the illustration) (5) through the bypass capacitors back to the +VS connection of the laser diode. The inductance of this loop can be minimized by placing the laser as close to the AD9661A as possible to keep the loop short, and by placing the send and return paths on adjacent layers of the PC board to take advantage of mutual coupling of the path inductances. This mutual coupling effect is the most important factor in reducing inductance in the current path. The trace from the output pins of the AD9661A to the cathode of the laser should be several millimeters wide and should be as direct as possible. The return current will choose the path of least resistance. If the return path is the GROUND plane, it should have an unbroken path, under the output trace, from the laser anode back to a the AD9661A. If the return path is not the ground plane (such as on a two layer board, or on the +VS plane), it should still be on the board plane adjacent to the plane of the output trace. If the current cannot return along a path that follows the output trace, the inductance will be drastically increased and performance will be degraded.
In applications where the dynamic performance of the analog feedback loop is important, it is necessary to optimize the layout of the gain resistor, RGAIN, as well as the monitor current path to SENSE IN. Such applications include systems which recalibrate the write loop on pulses as short as 25 ns, and closed-loop applications. The best possible TZA settling will be achieved by using a single carbon surface mount resistor (usually 5% tolerance) for RGAIN and small surface mount capacitor for CGAIN. Because the GAIN pin (Pin 5) is essentially connected to the inverting input of the TZA, it is very sensitive to stray capacitance. RGAIN should be placed between Pin 5 and Pin 6, as close as possible to Pin 5. Small traces should be used, and the ground and +VS planes adjacent to the trace should be removed to further minimize stray capacitance. The trace from SENSE IN to the anode of the PIN photodetector should be thin and routed away from the laser cathode trace.
Example Calculations
The example below (in addition to the one included in the sections above) should guide users in choosing RGAIN, CGAIN, the hold capacitor values, and worst case calibration times. System Requirements: * Laser power: 4 mW 2% * Hold Time: 0.5 ms Laser diode/photo diode characteristics: * Laser efficiency 0.3 mW/mA * Monitor current : 0.2 mA/mW * From the laser power requirements and efficiency we can estimate:
IOUT
MAX
mW = 4 mW x (2.0%)/ 0.3 = 266.6 A. mA
+VS PLANE
PIN ASSIGNMENTS OUTPUT PIN CONNECTIONS 26 25 1 2 5
BYPASS CAPS
AD9661A
24 23 22 MUTUAL COUPLING REDUCES INDUCTANCE
3
21 20 19 GROUND PLANE
GROUND PIN CONNECTIONS 4
LASER DIODE CURRENT PATH SEGMENTS (See Text)
Figure 6. Laser Diode Current Loop
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* Choosing a hold caps based on this:
CHOLD =
18 x10 -9 x 0.5 ms = 0.034 F 266.6 A
* From the monitor current specification and the max power specified: I MONITOR MAX = 4 mW and 0.2 mA mW = 800 A
* The initial calibration time for < 0.1% error: 7 = 7 x RC = 7 x 550 x 0.034 F = 130.9 s * Recalibration for a 0.1% error after 2% droop (need to correct within 5%): 3 = 3 RC = 3 x 140 x 0.034 F = 14.28 s
RGAIN =
1.6 V I MONITOR MAX
- 50 = 2.0 k
* CGAIN would be chosen from the table as 3 pF for safe compensation.
Typical Performance Characteristics
PULSE INPUT (TTL)
LASER POWER 20mV/DIV
20ns/DIV
LASER POWER 20mV/DIV
1ns/DIV
Figure 7. Driving 78N20 Laser Diode @ 5 mW
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AD9661A-Typical Performance Characteristics
180 4.2 160 140 120
IOUT - mA
100 80 60 40 20
10mV
0 1.7 2 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4
20ns
VHOLD - V
+5V
Figure 8. Typical AD9661A V/I Transfer Function
AD9661A
2pF 3V 2V LOW HIGH 1k POWER MONITOR GAIN POWER LEVEL PULSEL
1k HOLD 33pF
10 TO SCOPE MPSH81
SENSE IN OUTPUT
Figure 9. Typical AD9661A Closed-Loop Pulse Response
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AD9661A EVALUATION BOARD
The AD9661A Evaluation Board is comprised of two printed circuit boards. The Laser Diode Driver (LDD) Resource Board is both a digital pattern generator and an analog reference generator (see LDD Resource Board Block Diagram.) The board is controlled by an IBM compatible personal computer through a standard printer cable. The resource board interfaces to the AD9661A DUT board, which contains the AD9661A, a level shift circuit for the analog input, and a socket for an N type
laser diode. A dummy load circuit for the laser diode is included for evaluation. Power for all the boards is provided through the banana jacks on the AD9661A DUT board. These should be connected to a linear, +5 V power supply. Schematics for the LDD Resource Board, AD9661A DUT, and Dummy Load are included, along with a bill of material and layout information. Please contact Applications for additional information.
40MHz CLOCK OSCILLATOR STANDARD PARALLEL PRINTER CABLE P1 IBM-COMPATIBLE PC WITH WINDOWS PARALLEL PRINTER PORT CENTRONICS CONNECTOR READBACK LATCH
32K x 16 MEMORY PULSE WIDTH MODULATOR (AD9560) ADDRESS COUNTER AND RESOURCE CONTROLLER
OUTPUT SMB CONNECTORS
J4 J5 J7 J8 J6 J2
PULSE1 (JPUL) CAL (JCALB) DISABLE (JDIS) PULSE2 (JPULB) UNUSED TRIGGER J3
OUTPUT BUFFER
DIGITAL PATTERN GENERATOR
INTERFACE TO AD9661A EVALUATION BOARD
8
DAC 1
X1
0-2.55V
12 11
EXTERNAL LEVEL SHIFT CIRCUIT R9 AD9661A R8 LEVEL SHIFT IN +5V POWER SUPPLY GROUND
8
DAC 2
X1
0-2.55V 20-PIN HEADER 17-20 1-10
ANALOG REFERENCE LASER DIODE DRIVER RESOURCE BOARD
Figure 10. LDD Resource Board Block Diagram
INPUT SMB CONNECTORS FOR DIGITAL CONTROLS 5
AD9661A
DUMMY LOAD CIRCUIT/ LASER DIODE SOCKET
20 20-PIN HEADER FOR ANALOG CONTROLS OPTIONAL LEVEL SHIFT CIRCUIT
AD9661A
EVALUATION BOARD
Figure 11. Evaluation Board Block Diagram
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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Plastic SOIC (R-28)
C2079-6-10/95
0.013 (0.33) 0.009 (0.23) 0.04 (1.02) 0.024 (0.61) 0.712 (18.08) 0.700 (17.78)
28 15
0.300 (7.60) 0.292 (7.40)
1 14
0.419 (10.64) 0.393 (9.98)
PIN 1 0.104 (2.64) 0.093 (2.36) 0.0500 (1.27) BSC 0.019 (0.48) 0.014 (0.36) SEATING PLANE
0.012 (0.30) 0.004 (0.10)
-12-
REV. 0
PRINTED IN U.S.A.

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